logo
down
shadow

Assembly memory operands clarification


Assembly memory operands clarification

By : user2955495
Date : November 22 2020, 10:40 AM
should help you out I understand when for example [BX] is in between brackets it is referring to its memory contents. But at the same time I do not understand that.
code :
CMP [BX], 12ADH
CMP WORD [BX], 12ADH
MOV EBX, [BX]
         Memory             Register File
           ...
        _________             ________
 100h  |  1234h  |     /---- |  102h  | BX
       |_________|     |     |________|
 102h  |  5678h  | <---/        ...
       |_________|
 104h  |  9ABCh  |
       |_________|
 106h  |  DEF0h  |
       |_________|
           ...


Share : facebook icon twitter icon
x86 assembly memory operands

x86 assembly memory operands


By : user2551385
Date : March 29 2020, 07:55 AM
wish help you to fix your issue Yes, the register that is used as an operand resolves the ambiguity. (Note, however, that ax is a 16-bit register, not an 8-bit register -- that would be ah or al for the high or low byte, respectively.)
If you're only referring to memory operands, you need to use a BYTE PTR, WORD PTR or DWORD PTR specifier to resolve the ambiguity, like this:
code :
mov dword ptr [eax], 0
Manual Null-Termination on Unix using Intel x86 Assembly (address vs value in memory operands)?

Manual Null-Termination on Unix using Intel x86 Assembly (address vs value in memory operands)?


By : Jabez Sam
Date : March 29 2020, 07:55 AM
help you fix your problem I have to be missing something obvious here, but I can't seem to find the end of a string. , Two problems with your code:
code :
mov     byte[esi + rlen], 92
; read(2) return value still in eax

test eax, eax
jl  read_error    ; handle errors on eax less than zero.

mov esi, buf      ; mov imm32 to get the address in a register

mov  [rlen], eax  ; store return value to the rlen global

mov  byte ptr[esi + eax], 0
;or:  mov byte ptr [buf + eax], 0  ; works because the buffer is statically allocated.

jz  handle_EOF    ; flags still set from test
Referencing memory operands in .intel_syntax GNU C inline assembly

Referencing memory operands in .intel_syntax GNU C inline assembly


By : dinesh kumar
Date : March 29 2020, 07:55 AM
will be helpful for those in need
I don't believe Intel syntax uses the percent sign. Perhaps I am missing something?
code :
int libtest_intel()
{
    uint32_t rnds_00_15;
    // Intel syntax operand-size can only be overriden with operand modifiers
    // because the expansion includes an explicit DWORD PTR
    __asm__ __volatile__
    (  // ".intel_syntax noprefix \n\t"
        "mov %[rnds_00_15], 1  \n\t"
        "cmp %[rnds_00_15], 1  \n\t"
        "je  .Ldone%=                 \n\t"
        ".Ldone%=:                    \n\t"
        : [rnds_00_15] "=&m" (rnds_00_15)
        :
        : // no clobbers
    );
    return 0;
}
libtest_intel:
    mov DWORD PTR [rsp-4], 1  
    cmp DWORD PTR [rsp-4], 1  
    je  .Ldone8                 
.Ldone8:                    

    xor     eax, eax
    ret
#include <stdint.h>
int libtest_override_operand_size()
{
    uint32_t rnds_00_15;
    // Intel syntax operand-size can only be overriden with operand modifiers
    // because the expansion includes an explicit DWORD PTR
    __asm__ __volatile__
    (
        "{movl $1, %[rnds_00_15] | mov %[rnds_00_15], 1}  \n\t"
        "{cmpl $1, %[rnds_00_15] | cmp %k[rnds_00_15], 1}  \n\t"
        "{cmpw $1, %[rnds_00_15] | cmp %w[rnds_00_15], 1}  \n\t"
        "{cmpb $1, %[rnds_00_15] | cmp %b[rnds_00_15], 1}  \n\t"
        "je  .Ldone%=                     \n\t"
        ".Ldone%=:                        \n\t"
        : [rnds_00_15] "=&m" (rnds_00_15)
    );
    return 0;
}
     mov DWORD PTR [rsp-4], 1  
     cmp DWORD PTR [rsp-4], 1  
     cmp WORD PTR [rsp-4], 1  
     cmp BYTE PTR [rsp-4], 1  
    je  .Ldone38                     
.Ldone38:                        

    xor     eax, eax
    ret
    movl $1, -4(%rsp)   
    cmpl $1, -4(%rsp)   
    cmpw $1, -4(%rsp)   
    cmpb $1, -4(%rsp)   
    je  .Ldone38                     
.Ldone38:                        

    xorl    %eax, %eax
    ret
x86-64 assembly order of operands

x86-64 assembly order of operands


By : biqian
Date : March 29 2020, 07:55 AM
hop of those help? It depends on the syntax of an assembler. Mostly we have two choices: Intel and AT&T syntaxes.
There are multiple flavours of Intel syntax, the major ones being NASM (mov dword [symbol_name], 1) and MASM (including GAS's .intel_syntax noprefix mode which many GNU and Unix tools can use.) See https://stackoverflow.com/tags/intel-syntax/info for details on the differences and telling them apart.
code :
push   rbp         # comment character can be # (GAS) or ; MASM/NASM
mov    rbp,rsp
mov    DWORD PTR [rbp-0x4],edi
mov    DWORD PTR [rbp-0x8],esi
mov    edx,DWORD PTR [rbp-0x4]
mov    eax,DWORD PTR [rbp-0x8]
add    eax,edx
pop    rbp
ret

add    dword ptr [rdi], 1    # size specifier mandatory if neither operand is a reg
imul   ecx, [rdi + rax*4 + 20], 12345
push   %rbp                 # comment character is always #
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    -0x4(%rbp),%edx
mov    -0x8(%rbp),%eax
add    %edx,%eax
pop    %rbp
retq

addl  $1, (%rdi)      # size suffix b/w/l/q used to indicate operand-size if neither operand is a register

# with more than 2 operands, reverse the whole list
imul   $12345, 20(%rdi, %rax, 4), %ecx 
Understanding GCC inline assembly code that uses memory source operands and x87 fcomi / fcmov

Understanding GCC inline assembly code that uses memory source operands and x87 fcomi / fcmov


By : Roger Noguera
Date : October 07 2020, 06:00 PM
this one helps. You probably want to replace this inline asm instead of even trying to fix and/or improve it. You mentioned something about "secure", so many non-data-dependent performance to avoid timing side channels? You might want to ensure branchless code.
I'd suggest using intrinsics for _mm_max_ss (SSE1) if you want to make sure the compiler uses that. But really a ternary will reliably compile to branchless code. What is the instruction that gives branchless FP min and max on x86?
code :
float findmax_asm(const float *arr, size_t len)
{
    float maxval = -INFINITY;
    for (size_t i=0 ; i<len ; i++) {
        float val = arr[i];
        float temp;
        asm volatile("fld %2 \n"
              "fld %3 \n"
              "fcomi \n"
              "fcmovbe %%st(1), %%st \n"
              "fstp %0 \n"
              "fstp %1 \n"
              :"=m"(maxval), "=m"(temp)
              :"m"(val), "m"(maxval));
    }
    return maxval;
}
.L20:
        flds    (%eax)  # MEM[base: _18, offset: 0B]
        fstps   8(%esp)       # val

## inline asm starts here
        fld 8(%esp)     # val
fld 4(%esp)     # maxval               # st(0) = maxval,  st(1) = val
fcomi                                 # implicitly %st(1), %st  i.e.  fcomi val, maxval
fcmovbe %st(1), %st                   # copy if maxval<=val
fstp 4(%esp)    # maxval              # store updated maxval back to memory
fstp 12(%esp)   # temp                # and uselessly store temp = val
## and ends here

        addl    $4, %eax        #, ivtmp.25
        cmpl    %edx, %eax      # _25, ivtmp.25          # induction-variable temporary pointers invented by the compiler to turn arr[i] into a pointer-increment
        jne     .L20      #,                           # }while(p != endp);

# loop ends with maxval in memory.

        flds    4(%esp) # maxval
.L23:
        addl    $16, %esp       #,
        ret                                            # with %st = maxval return value
maxval = (val < maxval) ? maxval : val;
#include <stdint.h>
#include <stdlib.h>
#include <math.h>

float findmax_c(const float *arr, size_t len)
{
    float maxval = -INFINITY;
    for (size_t i=0 ; i<len ; i++) {
        float val = arr[i];
        maxval = (val < maxval) ? maxval : val;  // maxss (mem), reg
    }
    return maxval;
}
.L4:
        flds    (%eax)  # MEM[base: _1, offset: 0B]
        fxch    %st(1)      #
        fcomi   %st(1), %st   #,
        fcmovbe %st(1), %st       #,,
        fstp    %st(1)      #
        addl    $4, %eax        #, ivtmp.9
        cmpl    %eax, %edx      # ivtmp.9, _5
        jne     .L4       #,
        ret     
shadow
Privacy Policy - Terms - Contact Us © ourworld-yourmove.org