 c makefile with shell commands and variables
By : hertizonical
Date : March 29 2020, 07:55 AM
This might help you Remember that every command is run in its own shell, so dateString and revision will be unset in third and fourth command. So you use semicolons and backslashes at each line's end to make it one command. Also you need to use $$ to refer to shell's $. code :
version.h:
echo \#define VERSION_DATE \"$$(date +%Y/%m/%d\ %H:%M:%S)\" > version.h.tmp
echo \#define VERSION_REVISION \"$$(svn info | grep Revision | tr -d [:alpha:]:)\" >> version.h.tmp
mv version.h.tmp version.h
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 How to use shell commands in Makefile
By : Ryan Bennett
Date : March 29 2020, 07:55 AM
Hope that helps I'm trying to use the result of ls in other commands (e.g. echo, rsync): , With: code :
FILES = $(shell ls)
FILES = $(shell ls)
all:
echo $(FILES)
all:
FILES="$(shell ls)"
FILES="$(shell ls)"; echo $$FILES
echo *
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 How to execute shell commands in Automake/Makefile.am?
By : Theodore Yo
Date : March 29 2020, 07:55 AM
help you fix your problem POSIX make and many specific make implementations provide no mechanism for running shell commands outside of recipes. GNU make and perhaps others do provide that as an extension, but one of the objectives of the Autotools is to support the widest variety of build environments possible, so relying on extensions provided by specific implementations is contrary to Autotools idiom. One way to approach the problem without relying on extensions would be to make your sources #include a header that is generated dynamically at build time. For example, here's how the Makefile.am part might look: code :
bin_PROGRAMS = hello
hello_SOURCES = \
hello.cpp \
build_details.h
BUILT_SOURCES = \
build_details.h
CLEANFILES = \
build_details.h
build_details.h:
echo "#define BUILDDATE \"`date +%D`\"" >$@
echo "#define COMPILER \"$(CXX)\"" >>$@
bin_PROGRAMS = hello
builddate := $(shell date +%D)
CXXFLAGS = -DBUILDDATE='"$(builddate)"' -DCOMPILER='"$(CXX)"'
hello_SOURCES = \
hello.cpp
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How to change PATH for Makefile $(shell ...) commands?
By : user2425017
Date : March 29 2020, 07:55 AM
help you fix your problem Is this with GNU make? There is a long-standing GNU make feature request to honor exported variables with $(shell …). This is not specific to PATH at all, it affects (or does not affect) all export variables. According to the GNU make sources, this is tricky to implement: code :
/* Using a target environment for 'shell' loses in cases like:
export var = $(shell echo foobie)
bad := $(var)
because target_environment hits a loop trying to expand $(var) to put it
in the environment. This is even more confusing when 'var' was not
explicitly exported, but just appeared in the calling environment.
See Savannah bug #10593.
envp = target_environment (NULL);
*/
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Shell Commands Using ( on Makefile
By : Shankar Kumar
Date : March 29 2020, 07:55 AM
around this issue The problem is recipe commands are passed to /bin/sh which cannot process that syntax. You can change your Makefile to say: code :
clean:
bash -O extglob -c "rm -rf !(makefile|$(aula).tex|$(aula).pdf) -v"
make SHELL="/bin/bash -O extglob" clean
SHELL := /bin/bash -O extglob
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code :
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